A number of different transistor structures have been used for high power, high-frequency applications such as the metal-oxide semiconductor field-effect transistor (MOSFET), the metal-semiconductor field-effect transistor (MESFET) and the junction field-effect transistor (JFET). Junction field-effect transistors use the depletion region of a reverse-biased p-n junction to modulate the cross-sectional area of the device available for current flow. JFETs are predominantly majority carrier devices and are therefore advantageous for use in high speed applications because they do not suffer from minority carrier storage effects which would limit the range of frequencies over which these devices could operate.
In addition to the type of structure--and perhaps more fundamentally--the characteristics of the semiconductor material from which a transistor is formed also affects the operating parameters. Of the characteristics which affect a transistor's operating parameters, the electron mobility, saturated electron drift velocity, electric breakdown field and thermal conductivity have the greatest effect on a transistor's operating characteristics. These characteristics are further affected by the crystal polytypes of the semiconductor material used in the construction of the device. Furthermore, the number of defects in the crystalline semiconductor material affects the characteristics of the device as fewer defects generally produce higher quality devices.
Previously, JFETs have been manufactured of silicon (Si) or gallium arsenide (GaAs) because of their ease of manufacture. Although these devices provide increased operating frequencies, the relatively low breakdown voltage and the lower thermal conductivity of these materials limit their usefulness. For high power applications, previous Si or GaAs devices operating in the RF frequencies (up to 1.0 GHz) and in the 1-10 GHz microwave range have had limited power handling capability. Furthermore, previous devices were limited in the temperatures at which they could operate.
Alternatively, silicon carbide (SiC) has been known for many years to have excellent physical and electronic properties which should allow production of electronic devices that can operate at significantly higher temperatures than devices produced from silicon (Si) or GaAs. The most important of these properties are its wide bandgap (about 2.9 eV for 6H-SiC at room temperature), chemical inertness, and low dopant diffusivities. The combination of these properties make SiC well suited to high temperature electrical operation with low leakage currents, and minimal degradation due to diffusion or electromigration. The high electric breakdown field of about 4.times.10.sup.6 V/cm, high saturated electron drift velocity of about 2.0.times.10.sup.7 cm/sec, and high thermal conductivity of about 4.9 W/cm-K also indicates that SiC is a very promising material for high power, high frequency operation at elevated temperatures. Unfortunately, the low electron mobility and difficulty in manufacturing SiC devices has limited the usefulness of SiC in many of these applications.
Previously, 6H-SiC JFETs have been reported using epitaxially grown p-type 6H-SiC thin films, as thick as 20-30 .mu.m, grown on n-type 6H-SiC substrates (Dmitriev et al, Sov. Tech. Phys. Lett. 14(2) (1988); and Anikin et al, Pis'ma ZH. Tekh. Fiz. 15 (1989)). The use of an n-type substrate, however, results in buried gate layers which must be contacted from the top of the wafer using an etched window through the channel layer. A topside contact takes up a large area, making the die area larger, and it requires photolithography steps for etching the window and for patterning the gate contact. Additionally, spreading resistance loss associated with propagating the gate signal across the low mobility p-type epilayer can be especially detrimental to high frequency devices.
The use of a p-type substrate gate allows one to reduce the die size of the device (no topside gate contact) and depositing the ohmic contact to the backside of the wafer does not require any photolithography. The spreading resistance through the substrate is much less, by virtue of the large cross-sectional area of the die, as compared with the cross-sectional area of a p-type epilayer.
JFETs using p-type substrates have been reported by Kelner, et al, IEEE Trans. on Electron Dev., Vol. 36, No. 6 (1989). Kelner used a p-type 6H-SiC substrate that acted as the buried gate for .beta.-SiC epilayer. .beta.-SiC grown on 6H-SiC can include a high density of crystalline defects, however, known as double positioning boundaries (DPBs). These defects can contribute to high leakage currents in such films as compared with 6H-SiC grown on 6H-SiC.